In semiconductor devices, there has conventionally been used a silicon (Si) substrate. In recent years, wide-band gap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are attracting attention in the field of power semiconductor devices, and are being developed.
Wide-band gap semiconductors are semiconductor materials with a high degree of hardness that are wider in band gap than Si. Research is conducted to put into practical use various semiconductor devices that make use of the physical properties of wide-band gap semiconductors, such as power elements, environmentally-resistant elements, high-temperature operating elements, and high-frequency elements. Application of the wide-band gap semiconductors to power elements, in particular, such as switching elements and rectifier elements, is attracting attention, because the power elements that use SiC or GaN have advantages including a significant reduction in power loss as compared to that of Si power elements.
As the power elements using SiC or GaN, there have been reported a metal-insulator-semiconductor field effect transistor (hereinafter referred to as MISFET), a junction field effect transistor (hereinafter referred to as JFET), a p-n junction diodes, and a Schottky barrier diode. Such power elements may realize an on state where a current of several amperes (A) or higher flows and an off state where the current is zero while as high a withstand voltage of several hundred volts or higher is maintained.
The wide-band gap semiconductors may also maintain their semiconductor characteristics in a high-temperature environment, and great expectations are placed on SiC and GaN as a power element capable of operating in a high-temperature environment (for example, 200° C. or higher), which is not feasible with Si.
Those power elements are obtained by forming a plurality of elements on a wafer which is made mainly from a semiconductor and dividing the wafer into chips. Hereinafter, a wafer, before power semiconductor elements or the like are formed, is referred to simply as “wafer” and a wafer, on which power semiconductor elements or the like have been formed, is referred to as “semiconductor wafer”. The term wafer also includes one that has an epitaxial layer on the principal surface (front surface) or the rear surface.
In the case of a wafer made from a single-crystal semiconductor, a “cutout” called an orientation flat or a notch is provided in the circumference of the wafer in order to indicate the crystal orientation of the wafer. The orientation flats or notches in wafers are used in a semiconductor manufacturing process to align the crystal orientations of the wafers. This significantly reduces fluctuations in many semiconductor element characteristics that are dependent on the crystal orientation. The arrangement of semiconductor elements on a wafer is disclosed in, for example, Patent Document Nos. 1 to 6.
FIGS. 18(a) and 18(b) are schematic diagrams illustrating respectively a semiconductor wafer with orientation flats and a semiconductor wafer with a notch on which a plurality of square-shaped power semiconductor devices are arranged. As illustrated in FIG. 18(a), a semiconductor wafer 1001 includes a wafer that has an orientation flat 1001a and a second orientation flat 1001b and a plurality of power semiconductor devices 1010. Usually, the orientation flat 1001a and the second orientation flat 1001b are orthogonal to each other, and the plurality of the power semiconductor devices 1010 are formed on the wafer so that two sides of each of the plurality of the power semiconductor devices 1010 are parallel to the orientation flat 1001a and the second orientation flat 1001b. 
A direction determined by the orientation flat 1001a is defined herein as a direction parallel to the orientation flat 1001a (the orientation flat longer in the straight line direction) as indicated by an arrow 1005 of FIG. 18(a).
As illustrated in FIG. 18(b), a semiconductor wafer 1001′ includes a wafer that has a notch 1001c and a plurality of power semiconductor devices 1010. The plurality of power semiconductor devices 1010 are formed on the wafer so that one side of each of the plurality of power semiconductor devices 1010 is parallel to a direction of an arrow 1005′ which is determined by the cutout of the notch 1001c. 
Arranging the plurality of power semiconductor devices 1010 cyclically on the wafer facilitates the separation of the power semiconductor devices 1010 from one another. The power semiconductor devices 1010 are separated from one another along orthogonal cutting lines (hereinafter also referred to as scribe lines) 1020x and 1020y. Usually, unless there are no restrictions in shape, semiconductor chips which are obtained by separating the power semiconductor devices 1010 from one another each having a substantially square shape on a plane parallel to the front surface of the original semiconductor wafer 1001 or 1001′.